Show HN: Esp32sim – Run ESP32 Firmware In The Browser

TL;DR

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Esp32sim is an open-source Rust emulator that runs firmware for four ESP32 SoCs, spanning Xtensa and RISC-V processors, in a browser through WebAssembly. Its developer says it can boot real ROM, bootloader and unmodified application images; the project also reports hardware comparisons, with different test limits and maturity across chips.

The developer of Esp32sim has released a browser-based emulator for firmware targeting four Espressif ESP32 chips, using WebAssembly to run the software locally in a web page. The open-source Rust project says it boots each chip’s real mask ROM and second-stage bootloader, then runs unmodified application images—an approach that could make firmware experiments and demonstrations easier to access without physical boards or a local emulator setup.

The emulator supports the ESP32 and ESP32-S3, which use Espressif’s Xtensa processors, as well as the ESP32-C3 and ESP32-C6, which use RISC-V cores. The project provides a browser demo and command-line binaries. Its source describes the project as MIT-licensed and says no account or cloud service is required to try the browser version.

Esp32sim models enough hardware to run more than a bare CPU simulation. The project describes support for peripherals including GPIO, UART, timers, SPI flash and cryptographic hardware, alongside chip-specific features. Its S3 boards include display and input options, while the C3 browser demo is described as console-only. The C6 model includes an 802.15.4 energy-detection stand-in. Board models can add displays, buttons and other hardware behavior to the emulated system.

The repository reports several different kinds of validation, which should not be treated as a single guarantee of complete hardware equivalence. Its manual full-listing decoder checks report zero mismatches across 977,000 instructions for the S3, 161,000 for the C3 and 126,000 for the C6. Separate hardware comparisons report console output matching 205 of 208 lines for the C3 and 203 of 204 for the C6; the S3 comparison used a JTAG trace. The project says these are earlier manual runs, while continuous integration runs checked-in sampled decoder corpora and golden-output tests—not the external full-listing checks.

A Browser Route to Firmware Testing

Running firmware in a browser can lower the setup barrier for people who want to inspect an embedded project, reproduce a demonstration or learn how a board behaves. Users can try the supplied examples without first acquiring an ESP32 board, installing a toolchain or configuring a local emulator. That makes the project relevant to education, early prototyping and software demonstrations, especially when a physical device is not immediately available.

The potential benefit has limits. A simulated board does not reproduce every electrical condition, peripheral quirk or timing interaction of real hardware. Esp32sim’s reported comparisons show that the project tests its models against real devices in some cases, but the counts and methods vary by chip. Developers still need to verify behavior on the target hardware before relying on an emulated result for a product or deployment.

The project’s multi-chip scope also matters: supporting both Xtensa and RISC-V platforms gives users a common way to try firmware across several ESP32 families. However, support is not described as equally mature. The repository calls the S3 mature and labels the C3 and C6 implementations drafts, so users should check each chip’s documentation and known limitations.

Four Chips, Two Processor Families

Espressif’s ESP32 family includes devices built around different processor architectures and hardware configurations. Esp32sim handles the Xtensa-based ESP32 and S3 separately from the RISC-V-based C3 and C6, while sharing a number of modeled peripheral components across the emulator. The repository says the C3 and C6 reuse peripheral models where their hardware IP is identical, but each has its own memory and interrupt-related models.

The project is not presented as a new ESP32 hardware product. Its development is an emulator release, with a Rust codebase, a WebAssembly wrapper for browsers and a web interface for interacting with simulated boards. The repository lists demonstrations including Linux on the S3, display and audio projects, a camera example and Wi-Fi-related firmware. These are project examples, not independent evaluations of the emulator’s completeness.

For the S3, the project reports a block interpreter and an AArch64 just-in-time compiler, with claimed performance of about 150–240 million instructions per second. The C3 and C6 currently use interpreters without a block cache or JIT, though the repository says they run a hello-world example faster than real time. These figures are project-reported performance results and should be read in that context.

“Each boots the real mask ROM, the real 2nd-stage bootloader and an unmodified application image.”

— Esp32sim project documentation

Validation Limits and Chip Status

The supplied project material does not establish how the emulator performs across the full range of ESP32 firmware, board configurations or peripheral combinations. It also does not provide an independent assessment of the browser build’s compatibility across browsers and devices. The reported decoder and hardware results are project-reported tests, not an external certification of accuracy.

The hardware comparison figures have qualifications. The repository says the S3 JTAG trace comparison resynchronizes delay loops and normalizes window exceptions, so it is not uninterrupted cycle-by-cycle agreement. The C3 and C6 figures are console-line comparisons, and the project notes that manual full-listing tests are excluded from CI. The exact extent of peripheral coverage and behavior that remains incomplete should be checked in the chip-specific documentation; the C3 and C6 are marked as drafts.

Try the Demo and Track Tests

Readers can try the browser build through the project’s GitHub Pages demo or inspect the Rust source and chip-specific documentation in the repository. Developers seeking repeatable checks can review the checked-in golden-output tests and examples, then compare results on physical hardware where behavior matters. The project material supplied here does not give a dated roadmap or announce a next release milestone, so future feature additions and changes to C3 or C6 status remain unknown.

Key Questions

What is Esp32sim?

Esp32sim is an open-source emulator written in Rust that models four ESP32 SoCs and can run firmware in a browser through WebAssembly or from command-line tools.

Which ESP32 chips does it support?

The repository lists the ESP32, ESP32-S3, ESP32-C3 and ESP32-C6. The S3 implementation is marked mature, while the C3 and C6 implementations are described as drafts.

Does the browser version require an account or installation?

The project says the browser demo requires no account or cloud service and can be tried without installing the command-line emulator. A browser and internet access to load the demo are still needed.

Can Esp32sim replace testing on a physical board?

Not on the evidence provided. The project reports comparisons with real hardware, but those tests have stated limits and do not cover every firmware or peripheral. Physical-device testing remains appropriate when exact hardware behavior matters.

How reliable are the reported test results?

The results are reported by the project. Continuous integration runs sampled decoder tests and emulator golden outputs; the repository says the cited full-listing decoder checks were manual and are not part of CI.

Source: hn